1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, it relates to a method for trench isolation;
2. Description of the Related Art
One example of conventional methods for trench isolation is shown by a sectional view of a process in FIG. 4.
In the first place, as shown in FIG. 4(a), a silicon dioxide film 202 and a silicon nitride film 203 are successively formed on a silicon semiconductor substrate 201, and a resist pattern 207 is then formed in an area, where will become an element region, by the use of a lithography technique.
Next, as shown in FIG. 4(b), unnecessary portions of the silicon nitride film 203 and the silicon dioxide film 202 are etched and removed through the resist pattern 207 as a mask by the use of an anisotropic dry etching technique. Afterward, the resist pattern 207 is removed.
Next, as shown in FIG. 4(c), the silicon substrate 201 is vertically etched to a predetermined depth through the silicon nitride film 203 as an etching mask by the use of the anisotropic dry etching technique, thereby forming trenches 208.
Afterward, as shown in FIG. 4(d), a silicon dioxide film 212 is formed all over by the use of a chemical vapor deposition (CVD) method. The thickness of this silicon dioxide film 212 must be at least thicker than the depth of the trenches 208.
On the other hand, the step coverage of a silicon dioxide film by CVD method which has now been used does not attain 100%, so that the thickness of the silicon dioxide film deposited on a sidewall is smaller than that of the silicon dioxide film deposited on a horizontal face. In addition, a velocity at which the silicon dioxide film is deposited on the corner of a step is higher than a velocity at which it is deposited on a side face. Consequently, in the conventional technique, a void 213 is inconveniently formed in each of the trenches 208 during a step of burying the silicon dioxide film 212 into the trenches 208.
Next, as shown in FIG. 4(e), the whole surface of the substrate is polished back by a chemical mechanical polishing (hereinafter referred to as "CMP") method. In this case, a polishing amount is at least such that the previously formed and deposed silicon nitride film 203 is exposed but is not lost. By this polishing, a part of the void 213 in the trench might be exposed on the silicon dioxide film.
Lastly, as shown in FIG. 4(f), the silicon nitride film 203 and the silicon dioxide film 202 are successively removed by wet etching. By carrying out this wet etching, the thickness of the silicon dioxide film in the trenches is further decreased, so that the void 213 is more largely exposed. Moreover, if an etchant such as an aqueous hydrofluoric acid solution for the etching of the silicon dioxide film is put in the void 213, the void 213 is further etched, so that they might be enlarged.
As understood form the foregoing, when the trench isolation is done by the use of the conventional technique, voids or holes are formed in the silicon dioxide film with which the trenches are filled. If a gate electrode material is put in the voids, the conductive material in the voids cannot be removed completely at the time of gate etching, so that a short-circuit might occur between the gate electrodes.
The cause of this defect is that the deposition rate of the silicon dioxide film at the upper corners of the trenches is higher than that of the film on the side portions thereof. Therefore, the upper portions of the trenches are closed with the silicon dioxide film before the trenches are buried completely, so that the voids are formed in the trenches.
In order to solve the above-mentioned problem, a technique has been suggested which is described in Japanese Patent Application Laid-open No. 103446/1981. Here, this technique will be described in accordance with FIGS. 5(a) to 5(e).
In the first place, as shown in FIG. 5(a), a silicon dioxide film 204 and a silicon nitride film 205 are successively formed on a semiconductor substrate 201 obtained by the epitaxial growth of silicon on a silicon substrate. On this nitride film 205, a resist pattern 207 is then formed by a lithography technique.
Next, as shown in FIG. 5(b), the silicon nitride film 205, the silicon dioxide film 204 and the semiconductor substrate 201 are etched through the resist pattern 207 as a mask by the use of an anisotropic dry etching technique to form trenches 208. These trenches have an equal width in their sectional views.
Next, as shown in FIG. 5(c), the resist pattern 207 is removed by an ashing method or the like. Furthermore, the opening of the silicon dioxide film 204 is enlarged to a desired size with a hydrofluoric acid-containing agent. Afterward, anisotropic etching is carried out through the silicon dioxide film 204 as a mask by the use of a potassium hydroxide (KOH) solution or an ethylenediamine solution. At this time, silicon on the shoulder portions of the trenches 208 is removed therefrom, so that the upper portions of the sidewalls of the trenches 208 become slopes. In consequence, each trench comprises an equal width portion and a tapered upper portion continuous therewith in a sectional view.
The subsequent procedure is advanced in accordance with a usual process. That is to say, as shown in FIG. 5(d), a silicon dioxide film 212 is formed all over by the use of the CVD method to bury the trenches therewith, and the whole surface is polished back by the CMP method and the silicon nitride film 205 is then removed by wet etching. Next, the silicon dioxide film 204 is removed by the wet etching method to accomplish a trench isolation as shown in FIG. 5(e). According to this conventional technique, any voids are not formed any more in the vicinity of the surface of the silicon substrate in the step of burying the trenches 208 with the silicon dioxide film 212, because the upper portions of the trenches have an enlarged width.
For example, a pitch of a trench and an element region is represented by P as shown in FIG. 5(e). This pitch P is the sum of a trench width and an element region width represented by w, but the trench width and the element region width are usually decided as follows. That is to say, the trench width is required to be equal to or larger than a width which permits an electrical isolation. At this time, for example, in a layout of a memory such as a DRAM, a gate array or the like in which the high integration degree of an array is necessary, a minimum width which permits the electrical isolation is used as the trench width. Furthermore, the element region width is decided by the channel width of a transistor, the diameter of a contact hole connected to the element region and a distance between the contact hole and the edge of the element region. In general, it is required that the element region width is decreased to the utmost. Hence, the pitch P of the trench isolation and the element region is the sum of the minimum trench width and the minimum element region width just mentioned. Decreasing this pitch P is important to heighten the integration degree of the memory or the gate array.
However, this pitch P is now restricted by the limitations of a lithography technique in most cases. In other words, a resolution limit of a pitch pattern of the lithography technique is larger than the lower limit of the electrical pitch.
In this connection, a problem of the conventional technique is that when the pitch P for the trench isolation formed by the conventional technique shown in FIG. 5(e) is decreased to the limitations of the lithography technique, the width W of the element region is decreased because the upper portions of the trenches are obliquely etched. Furthermore, if it is attempted that a certain or more width W of the element region is obtained, the pitch P is required to be set in consideration of the oblique wide upper portions of the trenches. That is to say, the pitch for the trench isolation cannot be decreased to the limitations of the lithography technique. This reason is that the oblique upper portions of the trenches do not contribute to the essential element isolation and so they are unnecessary from the viewpoint of the electrical element isolation, but they are required to be formed only for the sake of preventing the voids from being formed in the trenches.